Plenary Talks
3D Integration Technology:
Status and Application Development
Dr. Peter Ramm
Fraunhofer IZM-M, Munich
Performance and productivity of microelectronics have increased continuously over more then four decades due to the enormous advances in lithography and device technology. However, today it has become questionable if this so-called “More Moore” development alone will be able to overcome the predicted performance and cost problems of future IC fabrication. The ITRS roadmap predicts 3D integration as a key technology to overcome this so-called “wiring crisis”. The corresponding solution will most probably be based on through silicon via (TSV) technology. Many institutes and companies have demonstrated full 3D integration processes. A large percentage of the process flows that are demonstrated early on in a technological evolution are usually feasible but are not commercially viable. Many of the process sequences shown may thus ultimately never reach commercialization. But which microelectronic products based on TSV technologies are at present actually in the market? CMOS image sensors using a “via last” approach with via diameters of about 50 µm and similar silicon thicknesses have been already introduced in the market mainly driven by form factor. In Europe STMicroelectronics developed a 2M pixel mobile-phone camera module VD6725 which is fabricated using TSV. The CMOS image sensor products are being fabricated in their Crolles facility.
In addition to the enabling of further improvement of transistor integration densities (“More Moore”), 3D integration is a well-accepted approach for so-called “More than Moore” applications with their essential need for integration of heterogeneous technologies. Wireless sensor systems represent a typical example for such heterogeneous systems demanding for smart system integration of ICs and MEMS/NEMS rather than extreme high transistor integration densities.
As considerable fraction of the world-wide activities, many European companies and research organizations are working currently in the area of 3D integration; several of them with a long-standing history and great expertise, as e. g. 3D-PLUS, Siemens, Infineon and Fraunhofer (since mid 1980´s). While the majority of the activities in Asia and in North America are targeting “More Moore” applications, the European industry will certainly benefit - from their strong background in microsystems technologies - of focusing on “More than Moore” products with their need of heterogeneous system integration: Heterogeneous combination of elements to integrate higher levels of intelligence into multifunctional microsystems including multisensing, processing, wireless and wired communication, and/or actuation capabilities. 3D integration is a very promising cost-effective approach for the realization of such heterogeneous systems.
The European 3D technology platform that has been established within the EC funded e-CUBES project [IST-026461] focussed on the requirements coming from heterogeneous systems. Seven corresponding technologies were successfully developed in all relevant categories of 3D Integration:
(1) 3D System-on-Chip (3D-SOC): Fraunhofer IZM-M´s TSV Technology (ICV-SLID) and SINTEF´s Hollow Via & Gold Stud Bump Bonding (HoViGo),
(2) 3D Wafer-Level Packaging (3D-WLP): IMEC / Fraunhofer IZM´s Thin-Chip-Integration Technology (TCI/UTCS) and CEA-LETI´s Via Belt Technology, and
(3) 3D System-in-Package (3D-SIP): 3D-PLUS´ High Performance Package-in-Package (HiPPiP) and Wireless Die-on-Die (WDoD) Technologies, as well as Tyndall´s Submicron Wire Anisotropic Conductive Film Technology (SW-ACF).
The 3D integration technologies which form part of the established e-CUBES platform will be presented including key characteristics, critical dimensions, electrical parameters and adaptability to new applications.